This course aims to convey a knowledge of advanced concepts of circuit design for digital VLSI components in state of the art MOS technologies. Emphasis is on the circuit design, optimization, and layout of either very high speed, high density or low power circuits for use in applications such as micro-processors, signal and multimedia processors, memory and periphery. Special attention will devoted to the most important challenges facing digital circuit designers today and in the coming decade, being the impact of scaling, deep submicron effects, interconnect, signal integrity, power distribution and consumption, and timing.
This semester, extra focus will be given to the following topics: Low power and low-voltage, process variations and robustness, and memory design in the nano scale era. This will reflected in both the lectures and the preferred projects.
J. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits: A Design Perspective , 2nd Edition, Prentice Hall, 2003.
1. S. Narendra and A. Chandrakasan, "Leakage in Nanometer CMOS Technologies", Springer, 2006.
2. B. Wong et al, "Nano-CMOS Circuit and Physical Design", Wiley, 2005.
3. C. Piguet Ed, "Low Power Electronics Design," CRC Press, 2004.
4. A. Chandrakasan, W. Bowhill, F. Fox, "Design of High-Performance Microprocessor Circuits", IEEE Press, 2001.
5. W.J. Dally and J.W. Poulton, "Digital System Engineering", Cambridge University Press, 1998.
6. K. Bernstein, et al, "High Speed CMOS Design Styles," Kluwer Academic Publishers, 1998.
7. V.G. Oklobdzija, "High-Performance System Design: Circuits and Logic," IEEE Press, 1999.
8. A. Chandrakasan and R. Brodersen, "Low-Power CMOS Design", IEEE Press, 1998.