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Ansoft Designer / Ansys Designer 在线帮助文档：

System Simulator >
System Component Models >
Digital Filters >
   Z-Domain Differentiator with Order M, K Stages (ZDIFFK)       

Z-Domain Differentiator with Order M, K Stages (ZDIFFK)

 

 


Property

Description

Units

Default

Range/Type

M

Filter order

None

35

[1, Inf)/Integer

K

Number of stages

None

1

[1, Inf)/Integer

RIN1

Input 1 impedance

Ohm

Inf

(0, Inf]/Real

RIN2

Input 2 impedance

Ohm

Inf

(0, Inf]/Real

ROUT

Output impedance

Ohm

0

[0, Inf)/Real

Ports

Input1

Input 1 signal (real)

Input2

Input 2 clock signal (real, optional)

Output

Output signal (real)

 

Notes

1. This model implements Z-Domain Differentiator with order M and K stages. I can be either clocked or non-clocked. If non-clocked, the second input port should be left open. The transfer function is of the form

[spacer]

 

Netlist form:

ZDIFFK:NAME n1 n2 n3 M=val [K=val] [RIN1=val] [RIN2=val]

+ [ROUT=val]

Netlist Example:

ZDIFFK:1 1 2 3 M=10 K=2



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