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Sample and Hold (SMPLHLD)

Sample and Hold (SMPLHLD)

Property	Description	Units	Default	Range/Type
DECAY_RATE	Output voltage decay rate, in 1/second unit	V/Sec	0	[0, Inf)/Real
RIN1	Input1 impedance	Ohm	Inf	(0, Inf]/Real
RIN2	Input2 impedance	Ohm	Inf	(0, Inf]/Real
ROUT	Output impedance	Ohm	0	[0, Inf)/Real
Ports
Input1	Input1 signal (real)
Input2	Input2 clock signal (real)
Output	Output signal (real)

Notes

1. The input signal is sampled at each rising edge of the clock signal (the input is sampled at the instant when the clock signal crosses a threshold of 0.5V). In the hold state of the sample and hold the output voltage decays at a constant rate determined by the parameter DECAY_RATE.

2. The output signal is always a baseband signal.

3. The input signal and output signal voltages of the SMPLHLD element, with its CLK pin tied to a clock source with period 10 msec and DECAY_RATE = 0, are shown in the figure below.

Netlist Form

SMPLHLD:Name n1 n2 n3 DECAY_RATE=val [Rin1=val] [Rin2=val] [Rout=val]

Netlist Example

SMPLHLD:1 1 2 3 DECAY_RATE=0

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