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Ansoft Designer / Ansys Designer 在线帮助文档：

System Simulator >
System Component Models >
Miscellaneous >
   Delay, Real Signal (RDELAY)       

Delay, Real Signal (RDELAY)

 

 


Property

Description

Units

Default

Range/Type

D

The number of samples by which the input signal is delayed

None

1

[0, Inf)/Integer

V

The value of the first D samples at the output

Volt

0.0

(-Inf, Inf)/Real

RIN

Input impedance

Ohm

Inf

(0, Inf]/Real

ROUT

Output impedance

Ohm

0

[0, Inf)/Real

Ports

Input

Input signal (real)

Output

Delayed input signal (real)

 

Notes

This model delays a real signal by a specified number of samples given by the parameter D. This delay will effectively place D samples of V at the beginning of the output signal.

Netlist Form

RDELAY:Name n1 n2 D=val [Rin=val] [Rout=val]

 

Netlist Example

RDELAY:1 1 2 D=8



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