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Ansoft Designer / Ansys Designer 在线帮助文档：

System Simulator >
System Component Models >
Frequency Synthesizers >
   Tri-State Phase Frequency Detector (PFDET)       

Tri-State Phase Frequency Detector (PFDET)

Notes

1. This element models the digital behavior of common D flip-flop type tri-state phase-frequency detectors often used in phase-locked loops.

2. The parameters VLin and VHin define the voltage level of the input signal. If an input signal is below VLin, it will be limited to VLin. If the signal is higher than VHin, it will be assumed to be VHin. The output level is set by VLout and VHout in a similar fashion.

3. The threshold at which the phase detector is triggered is determined by (VLin + VHin)/2.

4. This model can handle any type of input signals. The two inputs are usually from a reference oscillator and a divided VCO signal for phase-locked-loop applications.

5. In order to avoid large amount of time jitter and phase noise that would normally be introduced by not using a high enough sampling rate (higher sampling rate means slower simulation), the two output signals can be chosen to be amplitude modulated by setting AMMOD to 1. The so-called amplitude modulation works as follows: if based on the threshold-crossing line, the pulse width should be 1ms but the simulation timestep is 100ms, then the output amplitude or that timestep would be 1% of the VHout value. In detecting the pulse width, linear interpola­tion is used. Therefore, sawtooth waveforms are recommended.

6. The power spectrum of the noise contribution follows the equation L = Nc+ 10log(F_r) [1], where F_r is the reference frequency in PLL applications and Nc is a constant that is equivalent to the phase frequency detector noise with F_r = 1Hz.

7. When the parameter “NoiseOn” is set to 1, noise will be simulated. Otherwise, noise will not be incorporated.

Netlist Form

PFDET:Name n1 n2 n3 n4 VLin=val VHin=val VLout=val VHout=val
+ [AMMOD=Val] [Nc=Val] [Fr=Val] [Seed=Val] [RIN1=Val]
+ [RIN2=Val] [ROUT1=Val] [ROUT2=Val]

Netlist Example

PFDET:1 1 2 3 4 VLin=-1 VHin=1 VLout=0 VHout=1

References

1. Ulrich L. Rohde, David P. Newkirk, “RF/Microwave Circuit Design for Wireless Applica­tions.”

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