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System Simulator >
System Component Models >
Data Converters >
Parallel Analog to Digital Converter (PADC)

Parallel Analog to Digital Converter (PADC)

Property	Description	Units	Default	Range/Type
NBITS	Number of bits per sample	None	8	[1, 32]/Integer
VL	Minimum input voltage	Volt	-1	(-Inf, Inf)/Real
VH	Maximum input voltage	Volt	1	(-Inf, Inf)/Real
RIN1	Input impedance	Ohm	Inf	(0, Inf]/Real
RIN2	Input impedance	Ohm	Inf	(0, Inf]/Real
ROUT	Output impedance	Ohm	0	[0, Inf)/Real
Ports
Input1	Input signal (real)
Input2	Input clock signal (real) [Optional]
Output	Output signal (real)

Limits

1. VH> VL

Notes

1. The first input is supposed to be the analog signal to be sampled and quantized, while the second input is the clock signal. On the rising edge of the digital clock input to the parallel ADC, the input waveform is sampled and quantized. The number of quantization levels is equal to 2^nbits, with the range of input values being determined by vl and vh. Input signal values outside of this range will output 0 on the low side and (2^nbits-1) on the high side.

2. If a clock signal is not supplied on n2, the output is clocked out for every incoming sample.

Netlist Form

PADC:NAME n1 n2 n3 nbits=val vl=val vh=val [Rin1=val] [Rin2=val] [Rout=val]

Netlist Example

PADC:1 1 2 3 nbits = 8 vl = 0 vh = 1

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