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Ansoft Designer / Ansys Designer 在线帮助文档：

System Simulator >
System Component Models >
Microstrip >
   MS Via (MSVIAH, MSVIAH_Ref)       

MS Via (MSVIAH, MSVIAH_Ref)

 

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Properties

Description

Units

Default

Range

D

Diameter of upper VIA hole

m

Required

> 0

DG

Diameter of lower VIA hole

m

D

> 0

sub

Substrate name

none

Required

string

 

Notes

1. To get accurate results, the following condition should be satisfied: H << l, where:
l is the wavelength,
H is the substrate height defined in the .SUB statement.

2. If metallization is not specified (in the corresponding .SUB statement,) the VIA element behaves as an inductance only.

3. Radiation loss is included if the cover height is not defined in the .SUB statement.

Netlist Form

MSVIAH:NAME n1 [ n2 ] D=val [DG=val] SUB=label

Netlist Example

MSVIAH:VIA1 1 D=3.5MIL SUB=SUB1

where sub1 needs to be defined in the corresponding .sub statement.

References

1. Unpublished equations developed by Ansoft LLC.



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