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Ansoft Designer / Ansys Designer 在线帮助文档：

System Simulator >
System Component Models >
Miscellaneous >
Limiter (LIMITER)

Limiter (LIMITER)

Property	Description	Units	Default	Range/Type
VN	Negative output saturation voltage	Volt	-1	(-Inf, 0]/Real
VP	Positive output saturation voltage	Volt	1	[0, Inf)/Real
GAIN	Small signal voltage gain	None	10⁹	(-Inf, Inf)/Real
RIN	Input impedance	Ohm	Inf	(0, Inf]/Real
ROUT	Output impedance	Ohm	0	[0, Inf)/Real
Ports
Input	Input signal (complex)
Output	Output signal (complex)

Notes

1. This model performs amplitude limitation. If the input to this model is a baseband signal v_in(t), the output is a baseband signal. The output quadrature-phase is 0, and in-phase signal is given as follows
V_out,i(t) = GAIN . V_in(t), for VN £ GAIN . V_in,i(t) £ VP
V_out,i(t) = VN, for GAIN . V_in,i(t) < VN
V_out,i(t) = VP, for GAIN . V_in,i(t) > VP
V_out,q(t) = 0

If the input to this model is a bandpass signal with the in-phase and quad-phase envelopes V_in,i(t) and V_in,q(t), the output is bandpass signal and has the same carrier frequency as the input. The output in-phase and quad-phase envelopes are given as follows, respectively

V_out,i(t) = GAIN . V_in_,i(t) and V_out,q(t) = GAIN . V_in,q(t) for GAIN . V(t) < VP

V_out,i(t) = [VP/V(t)] .V_in_,i(t) and V_out,q(t) = [VP/V(t)]_·V_in_{, q}(t) for GAIN . V(t) ³ VP

where V(t) = SQRT(V_in,i(t)² +V_in,q(t)²)

Netlist Form

LIMITER:Name n1 n2 VN=val VP=val [GAIN=val] [Rin=val] [Rout=val]

Netlist Example

LIMITER:1 1 2 VN=-2V VP=2V GAIN=3

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