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Ansoft Designer / Ansys Designer 在线帮助文档：

System Simulator >
System Component Models >
Digital Logic >
   Latch (LATCH)       

Latch (LATCH)

 

 


Property

Description

Units

Default

Range/Type

RIN1

Input1 impedance

Ohm

Inf

(0, Inf]/Real

RIN2

Input2 impedance

Ohm

Inf

(0, Inf]/Real

ROUT

Output impedance

Ohm

0

[0, Inf)/Real

Ports

Input1

Input1 signal (real)

Input2

The clock signal (real)

Output

Output signal (real)

 

Notes


Function Table

Input (n1)

Clock (n2)

Output (n3)

L

H

L

H

H

H

x

L

Q0

x = don’t care state

L = logic low level; Inputs: <0.5; Outputs: 0.0

H = logic high level; Inputs: >0.5; Outputs : 1.0

Q0 = previous Q state


 

1. Initially, at time equal to 0 time units, the output Q is equal to L.

2. This element is clock level sensitive. If the user prefers a clock edge-triggered latch, the DFF element can be used with S=R=H.

3. The input, clock, and output signal voltages of the LATCH elements are shown.

Netlist Form

LATCH:Name n1 n2 n3 [Rin1=val] [Rin2=val][Rout=val]

Netlist Example

LATCH:1 1 2 3



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