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Ansoft Designer / Ansys Designer 在线帮助文档：

J-K Flip-Flop (JKFF)

Property	Description	Units	Default	Range/Type
RIN1	Input1 impedance	Ohm	Inf	(0, Inf]/Real
RIN2	Input2 impedance	Ohm	Inf	(0, Inf]/Real
RIN3	Input3 impedance	Ohm	Inf	(0, Inf]/Real
RIN4	Input4 impedance	Ohm	Inf	(0, Inf]/Real
ROUT1	Output1 impedance	Ohm	0	[0, Inf)/Real
ROUT2	Output2 impedance	Ohm	0	[0, Inf)/Real
Ports
Input1	The reset/clear signal (real)
Input2	The K input signal (real)
Input3	The Clock signal (real)
Input4	The J input (real)
Input5	The preset signal (real)
Output1	Output1 signal (real)
Output2	The inverted output signal (real)

Notes

Functional Table
Input					Output
R (n1)	K (n2)	C (n3)	J (n4)	S (n5)	Q (n6)	NQ (n7)
L	x	x	x	L	H	H
H	x	x	x	L	H	L
L	x	x	x	H	L	H
H	L	UP	L	H	Q0	NQ0
H	L	UP	H	H	H	L
H	H	UP	L	H	L	H
H	H	UP	H	H	Toggle
CLK = input clock, active with low to high transition S = input preset, active with logic low level R = input clear, active with logic low level x = don’t care state L = logic low level; Inputs: <0.5; Outputs: 0.0 H = logic high level; Inputs: >0.5; Outputs : 1.0 UP = low-to-high transition Q0 = previous Q state NQ = inverted Q state

1. Initially, at time equal to 0 time units, the outputs Q and NQ are equal to L and H, respectively.

2. The input (C, K, J) and output (Q) signal voltages of the JKFF element, with S and R both tied to a high logic level (1.0V), are shown.

JKFF:Name n1 n2 n3 n4 n5 n6 n7 [Rin1=Val] [Rin2=Val] [Rin1=Val] [Rin3=Val] [Rin4=Val] [Rin5=Val][Rout1=Val] [Rout2=Val]

JKFF:1 1 2 3 4 5 6 7


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