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Ansoft Designer / Ansys Designer 在线帮助文档：

System Simulator >
System Component Models >
Frequency Synthesizers >
   Frequency Divider (FREQDIV)       

Frequency Divider (FREQDIV)

 

 


Property

Description

Units

Default

Range/Type

N

Frequency Division Factor

None

1

(0, Inf)/Integer

SEED

Random seed

None

0

[0, Inf)/Integer

FLOOR

Noise floor in dB

None

-500

(-Inf, Inf)/Real

FLICKER

Divider flicker corner frequency

Hz

10000

(0, Inf)/Real

NOISEON

Noise: 1 for ON, 0 for OFF

None

1

[0, 1]/Integer

WAVETYPE

Incoming signal waveform type: 0 for sinusoid, 1 for sawtooth

None

0

[0, 1]/Integer

VPIN

Incoming signal peak voltage value (valid for sawtooth option)

Volt

1

(0, Inf)/Real

RIN

Input impedance

Ohm

Inf

(0, Inf]/Real

ROUT

Output impedance

Ohm

0

[0, Inf)/Real

Ports

Input

Input signal (complex)

Output

Output signal (complex)

 

Notes

1. This component models the frequency divider device. The division ratio is determined by the parameter N.

2. The input signal can be either of base-band sawtooth waveforms or envelope signals. When it is a sawtooth input signal, the user has to specify the corresponding peak voltage value “VPIN” of the incoming signal to make the model behave properly.

3. The parameters “FLOOR” and “FLICKER” are used to specify the noise characteristic of the divider device. When not needed, the noise simulation should be turned off by setting “NOISEON” to 0, this will normally speed up the simulation since it is expensive to simulate noise statistically.

4. In typical PLL applications, this model is used together with the reference oscillator to divide down the reference frequency (called R divider). Note, however, that using this component as a reference divider requires the use of base-band sawtooth waveforms.

Netlist Form

FREQDIV:Name n1 n2 N=val [SEED=val] [FLOOR=val] [FLICKER=val] [NOISEON=val] [WAVETYPE=val] [VPIN=val] [RIN=val]

+ [ROUT=val]

Netlist Example

FREQDIV:1 1 2 N=10 FLOOR=-160dB FLICKER=15000Hz WAVETYPE=1



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