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System Simulator > Delay Modulation (Miller Coding) Model (DLYMOD)
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NotesFor Delay modulation (Miller Coding), a high input value is represented by a transition at the midpoint of the bit interval. A low input value maintains the state value, unless two low input values occur in a row. When this happens, a transition occurs at the end of the bit interval.
Netlist FormADLYMOD:NAME n1 n2 Nexsys_component=dly_mod Level=val N=val [RIN=val] [ROUT=val] Netlist ExampleADLYMOD:1 1 2 Nexsys_component=dly_mod Level=2.2 N=2 Reference[1] Bernard Sklar, Digital Communications Fundamental and Applications, Prentice-Hall 1988
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