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System Simulator >
System Component Models >
Digital Logic >
Divide by N Counter (DIVN)

Divide by N Counter (DIVN)

Property	Description	Units	Default	Range/Type
N	Divide by factor	None	1	(0, Inf)/Integer
N0	Initial counter value	None	1	(0, N-1)/Integer
RIN	Input impedance	Ohm	Inf	(0, Inf]/Real
ROUT	Output impedance	Ohm	0	[0, Inf)/Real
Ports
Input	Input signal (real)
Output	Output signal (real)

Notes

1. This element is a model of a positive edge-triggered, modulo N down counter. The input to the element is a clock signal and the output is a signal that is high or low, depending on whether the current counter value is greater or less than floor (N/2). Note that the counter value itself is not available as an output.

Let M(k) denote the counter value after the kth positive clock edge. Then

M(0) = N0

M(k) = (M(k-1) -1) modulo N, k ³ 1

2. The initial counter value N0 is limited to the range [0, N-1] where N is the divide-by factor.

3. The input and output signal voltages of the DIVN element, with parameters N=7 and N0=1, are shown. Output is low until the first positive clock edge occurs at time 10 msec. Output jumps to high level at 10 msec, since initial counter N₀=1 (< floor (7/2) ).

4. Note that the period of the input signal is 10msec and the period of the output period is 70msec, which yields the signal frequency divided by 7 after the element.

Netlist Form

DIVN:Name n1 n2 [Rin1=Val] [Rout=Val]

Netlist Example

DIVN:1 1 2

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