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Ansoft Designer / Ansys Designer 在线帮助文档：

System Simulator >
System Component Models >
Coders/Decoders >
   Dicode RZ Formatting Model (DICRZ)       

Dicode RZ Formatting Model (DICRZ)

 

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Property

Description

Units

Default

Range/Type

Level

Output signal amplitude

Volt

1.0

[0, INF]/Real

N

Oversampling factor

None

1

[1, INF]/Real

RIN

Input impedance

Ohm

Inf

(0, Inf]/Real

ROUT

Output impedance

Ohm

0

(0, Inf]/Real

Ports

Input

Input sequence (real)

Output

Output sequence (real)

Notes

For Dicode RZ, a change in input state (0->1 or 1->0) will produce a half bit wide pulse of opposite polarity from the prior pulse transmitted. A half bit wide zero is transmitted to fill the bit wide time interval.

For no state change at the input (0->0 or 1->1), a bit wide zero voltage is transmitted. Initial refer­ence pulse is equal (-level) with 0 previous input.

 



 

Netlist Form

ADIC_RZ:NAME n1 n2 Nexsys_component=dic_rz Level=val N=val [RIN=val] [ROUT=val]

Netlist Example

ADIC_RZ:1 1 2 Nexsys_component=dic_rz Level=2.2 N=2

Reference

[1] Bernard Sklar, Digital Communications Fundamental and Applications, Prentice-Hall 1988



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