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System Simulator >
System Component Models >
Digital Logic >
   D Flip-Flop--Edge Triggered (DFF)       

D Flip-Flop--Edge Triggered (DFF)

 

 


Property

Description

Units

Default

Range/Type

RIN1

Input1 impedance

Ohm

Inf

(0, Inf]/Real

RIN2

Input2 impedance

Ohm

Inf

(0, Inf]/Real

RIN3

Input3 impedance

Ohm

Inf

(0, Inf]/Real

RIN4

Input4 impedance

Ohm

Inf

(0, Inf]/Real

ROUT1

Output1 impedance

Ohm

0

[0, Inf)/Real

ROUT2

Output2 impedance

Ohm

0

[0, Inf)/Real

Ports

Input1

The reset/clear signal (real, inverted)

Input2

The clock signal (real)

Input3

The D input signal (real)

Input4

The Preset signal (real, inverted)

Output1

The non-inverted output signal (real)

Output2

The inverted output signal (real)


 

Notes

 


Function Table

Input

Output

R (n1)

C (n2)

D (n3)

S (n4)

Q (n5)

NQ (n6)

H

x

x

L

H

L

L

x

x

H

L

H

L

x

x

L

H

H

H

UP

H

H

H

L

H

UP

L

H

L

H

H

Not UP

x

H

Q0

NQ0

S = input preset, active with low level

R = input clear, active with logic low level

C = input clock, active with low to high transition

D = input digital signal

x = don’t care state

L = logic low level. Input: < 0.5; Output: 0.0

H = logic high level. Input: > 0.5; Output 1.0

UP = low-to-high transition

Not UP = not an UP edge

Q0 = previous state

NQ inverted Q state

NQ0 = previous inverted Q state


The input, output and clock signal voltages of the DFF element, with S (n4) and R (n1) both tied to a high logic level (1.0 V), are shown in the figure below.

 

Netlist Form

DFF:Name n1 n2 n3 n4 n5 n6 [Rin1=val] [Rin2=val][Rin3=val] [Rin4=val][Rout1=val][Rou2t=val]

Netlist Example

DFF:1 1 2 3 4 5 6




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