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System Simulator >
System Component Models >
Miscellaneous >
Delay, Complex Signal (CDELAY)

Delay, Complex Signal (CDELAY)

Property	Description	Units	Default	Range/Type
D	The number of samples by which the input signal is delayed.	None	1	[0, Inf)/Integer
REAL_V	Real part of the value of the first D output samples	Volt	0	(-Inf, Inf)/Real
IMAG_V	Imaginary part of the value of the first D output samples	Volt	0	(-Inf, Inf)/Real
RIN	Input impedance	Ohm	Inf	(0, Inf]/Real
ROUT	Output impedance	Ohm	0	[0, Inf)/Real
Ports
Input	Input signal (complex)
Output	Output signal (complex)

Notes

This model delays a complex signal by a specified number of samples given by the parameter D. This delay will effectively place D number of samples at the beginning of the output signal with the value .

Netlist Form

CDELAY:Name n1 n2 D=val [REAL_V=val] [IMAG_V=val] [Rin=val] [Rout=val]

Netlist Example

CDELAY:1 1 2 D=8 REAL_V=1

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