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Terms in Designer > Glossary: E
Glossary: E
E2PROM (Electrically-Erasable Programmable Read-Only
Memory)
A memory device whose contents can be electrically
programmed by the designer. Additionally, the contents can be electrically
erased allowing the device to be reprogrammed. Also known as E2PROM.
EBE (Electron Beam Epitaxy)
A technique for creating thin films on substrates
in precise patterns, in which the substrate is first coated with a layer
of dopant material before being placed in a high vacuum. A guided beam
of electrons is fired at the substrate causing the dopant to be driven
into it, effectively allowing molecular-thin layers to be "painted"
onto the substrate where required.
ECL (Emitter-Coupled Logic)
Logic gates implemented using particular configurations
of bipolar junction transistors.
Edge port
A place in a layout or footprint geometry through
which excitation signals enter and leave the structure.
Edge-Sensitive
An input that only affects a function when it transitions
from one logic value to another.
EEPROM (Electrically-Erasable Programmable Read-Only
Memory)
A memory device whose contents can be electrically
programmed by the designer. Additionally, the contents can be electrically
erased allowing the device to be reprogrammed. Also known as EEPROM.
Electrically-Erasable Programmable Read-Only Memory
(EEPROM or E2PROM)
A memory device whose contents can be electrically
programmed by the designer. Additionally, the contents can be electrically
erased allowing the device to be reprogrammed.
Electromigration
(1)A process in which structures on an integrated
circuit's substrate are eroded by the flow of electrons in much the
same way as land is eroded by a river (also known as subatomic erosion).
(2)The process of forming transistor-like regions in a semiconductor
using an intense magnetic field.
Electron Beam Epitaxy (EBE)
A technique for creating thin films on substrates
in precise patterns, in which the substrate is first coated with a layer
of dopant material before being placed in a high vacuum. A guided beam
of electrons is fired at the substrate causing the dopant to be driven
into it, effectively allowing molecular-thin layers to be "painted"
onto the substrate where required.
Electron Beam Lithography
An integrated circuit fabrication process in which
fine beams of electrons are used to draw extremely high-resolution patterns
directly into the resist without the use of a mask.
Electro-Static Discharge (ESD)
The process of moving around can generate static electricity.
The term electro-static discharge refers to a charged person, or object,
discharging static electricity. Although the current associated with
such a static charge is low, the electric potential can be in the millions
of volts and can severely damage electronic components. CMOS devices
are particularly prone to damage from static electricity.
EM
Electromagnetic.
Emitter-Coupled Logic (ECL)
Logic gates implemented using particular configurations
of bipolar junction transistors.
Enzyme
One of numerous complex proteins which are produced
by living cells and catalyze biochemical reactions at body temperatures.
EPROM (Erasable Programmable Read-Only Memory)
A memory device whose contents can be electrically
programmed by the designer. Additionally, the contents can be erased
by exposing the die to ultraviolet light through a quartz window mounted
in the top of the component's package.
Equivalent Gate
A concept in which each type of logic function is
assigned an equivalent gate value for the purposes of comparing functions
and devices. However, the definition of an equivalent gate varies depending
on who you're talking to.
Equivalent Integrated Circuit
A concept used to compare the component density supported
by diverse interconnection technologies such as circuit boards, hybrids,
and multichip modules
Erasable Programmable Read-Only Memory (EPROM)
A memory device whose contents can be electrically
programmed by the designer. Additionally, the contents can be erased
by exposing the die to ultraviolet light through a quartz window mounted
in the top of the component's package.
ESD (Electro-Static Discharge)
The process of moving around can generate static electricity.
The term electro-static discharge refers to a charged person, or object,
discharging static electricity. Although the current associated with
such a static charge is low, the electric potential can be in the millions
of volts and can severely damage electronic components. CMOS devices
are particularly prone to damage from static electricity.
Etching
The process of selectively removing any material not
protected by a resist using an appropriate solvent or acid. In some
cases the unwanted material is removed using an electrolytic process.
Eutectic Bond
A bond formed when two pieces of metal, or metal-coated
materials, are pressed together and vibrated at ultrasonic frequencies.
Eye Diagram
An eye diagram of a signal overlays the signal waveform
over many cycles. Each cycle waveform is aligned to a common timing
reference, typically a clock. An eye diagram provides a visual indication
of the voltage and timing uncertainty associated with the signal. It
can be generated by synchronizing an oscilloscope to a timing reference.
The vertical thickness of the line bunches in an eye
diagram indicate the magnitude of AC voltage noise, whereas the horizontal
thickness of the bunches where they cross over is an indication of the
AC timing noise or jitter. Fixed DC voltage and timing offsets are indicated
by the position of the eye on the screen.
Eye Mask
The size of the eye opening in the center of an eye
diagram indicates the amount of voltage and timing margin available
to sample this signal. Thus, for a particular electrical interface,
a fixed reticule or window could be placed over the eye diagram showing
how the actual signal compares to minimum criteria window, know as the
eye mask. If a margin rectangle with width equal to the required timing
margin and height equal to the required voltage margin fits into the
opening, then the signal has adequate margins. Voltage margin can often
be traded off for timing margin.

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